1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to a damascene process for enhancing reliability in electrical connection among multi-layered wiring layers.
2. Description of the Related Art
As a semiconductor device is fabricated these days in higher integration and in a smaller size, a wiring layer is formed in a smaller size, and a multi-layered structure is selected in a greater number of semiconductor devices. As one of methods of fabricating a multi-layered structure, a damascene process is generally selected. A damascene process generally includes the steps of forming a via-hole or trench throughout an electrically insulating film formed on a substrate, depositing an electrically conductive material on the electrically insulating film such that the via-hole or trench is filled with the electrically conductive material, and applying chemical mechanical polishing (CMP) to the electrically conductive material to thereby form a via-contact or wiring in the via-hole or trench. A damascene process is suitable for fabricating a multi-layered structure composed of copper or an alloy thereof, because it is quite difficult to accurately etch a copper layer.
FIGS. 1A to 1F are cross-sectional views of a semiconductor device, illustrating respective steps of a via-first dual damascene process which is one of conventional damascene processes.
First, as illustrated in FIG. 1A, a first etching stopper layer 2 is formed on a substrate 1 on which a device such as a MOS transistor has been already fabricated. The first etching stopper layer 2 acts as an etching stopper to a later mentioned first wiring trench 3a. 
Then, a first interlayer insulating film 3 is formed entirely over the first etching stopper film 2.
Then, a resist film (not illustrated) is formed on the first interlayer insulating film 3, and then, is patterned.
Then, the first interlayer insulating film 3 and the first etching stopper layer 2 are dry-etched with the patterned resist film being used as a mask, to thereby form a first wiring trench 3a. 
Then, as illustrated in FIG. 1B, a barrier metal film 4 acting as an underlying film for a lower wiring layer is formed by sputtering entirely over the first interlayer insulating film 3 and an exposed area of the substrate 1.
Then, a seed metal film (not illustrated) is formed on the barrier metal film 4 by sputtering for facilitating growth of electroplated copper.
Then, copper 5a which will make a lower wiring layer is deposited over the barrier metal film 4 by electrolytic plating, as illustrated in FIG. 1B.
Then, the resultant illustrated in FIG. 1B is annealed at a temperature in the range of about 200 to 400 degrees centigrade to improve crystallinity of the copper 5a. 
Then, as illustrated in FIG. 1C, the copper 5a and the barrier metal film 4 are polished by chemical mechanical polishing (CMP) until the first interlayer insulating film 3 appears. Thus, there is formed a lower wiring layer 5 comprised of the copper 5a filling the first wiring trench 3a therewith.
Then, as illustrated in FIG. 1D, a first cap film 6 acting as a barrier for preventing diffusion of the lower wiring film 5, a via interlayer insulating film 7, a second etching stopper film 10 acting as an etching stopper to a later mentioned second wiring trench 11a, and a second interlayer insulating film 11 are formed in this order on the resultant illustrated in FIG. 1C.
Then, a resist film (not illustrated) is formed on the second interlayer insulating film 11, and then, is patterned.
Then, the second interlayer insulating film 11, the second etching stopper film 10 and the via interlayer insulating film 7 are etched with the patterned resist film being used as a mask, to thereby form a via-hole 9a throughout them.
Then, a resist film (not illustrated) is formed again on the second interlayer insulating film 11, and then, is patterned.
Then, the second interlayer insulating film 11 is etched with the patterned resist film being used as a mask, to thereby form a second wiring trench 11a throughout the second interlayer insulating film 11.
Then, the second etching stopper film 10 and the first cap film 6 are removed in their exposed areas.
Then, as illustrated in FIG. 1E, a barrier metal film 12 acting as an underlying film for an upper wiring layer is formed by sputtering entirely over the second interlayer insulating film 11, the via interlayer insulating film 7 and the exposed lower wiring layer 5.
Then, a seed metal film (not illustrated) is formed on the barrier metal film 12 by sputtering for facilitating growth of electroplated copper.
Then, copper 13a which will make an upper wiring layer is deposited over the barrier metal film 12 by electrolytic plating, as illustrated in FIG. 1E.
Then, the resultant illustrated in FIG. 1E is annealed at a temperature in the range of about 200 to 400 degrees centigrade to improve crystallinity of the electroplated copper 13a. 
Then, as illustrated in FIG. 1F, the copper 13a is polished by chemical mechanical polishing (CMP) until the second interlayer insulating film 11 appears. Thus, there are simultaneously formed an upper wiring layer 13 comprised of the copper 13a filling the second wiring trench 11a therewith, and a via-contact 9 comprised of the copper 13a filling the via-hole 9a therewith.
Thereafter, the steps having been explained with reference to FIGS. 1D to 1F are repeatedly carried out to thereby fabricate a semiconductor device having a desired multi-layered structure.
In the above-mentioned damascene process, the resultant illustrated in FIG. 1B or 1E is annealed at a temperature in the range of about 200 to 400 degrees centigrade before the copper 5a or 13a is polished by CMP, in order to improve crystallinity of the copper 5a or 13a filling the first wiring trench 3a, the via-hole 9a and the second wiring trench 11a therewith. The annealing carried out at such a high temperature results in residual tensile stress in the via-contact 9 or the first and second wiring layers 5 and 13 due to plastic deformation of the copper 5a or 13a, if the via-contact 9 or the first and second wiring layers 5 and 13 is returned back to a room temperature. Such residual tensile stress is of about 300 MPa. The residual tensile stress further causes a problem that the lower or upper wiring layer 5 or 13 is partially broken in the CMP process.
Even if the multi-layered structure as illustrated in FIG. 1F was packaged as a semiconductor chip, since residual tensile stress remains as it is in the lower or upper wiring layer 5 or 13, various defects due to stress migration, such as disconnection between the via-contact 9 and the upper wiring layer 13, may occur in the future.
Hereinbelow is explained disconnection caused by stress migration, with reference to FIGS. 2 and 3A to 3C. FIG. 2 is a cross-sectional view of a wiring structure, illustrating a defect which might occur in a wiring structure fabricated in accordance with a single damascene process, and FIGS. 3A to 3C are cross-sectional views of a wiring structure, each illustrating a defect which might occur in a wiring structure fabricated in accordance with a dual damascene process.
As illustrated in FIG. 2, residual tensile stress caused by annealing carried out at a high temperature remains in the lower wiring layer 5, the via-contact 9 and the upper wiring layer 13 in a wiring structure fabricated in accordance with a single damascene process. The residual tensile stress causes a problem that the copper moves in a direction indicated with arrows at the grain boundary 14 due to stress migration, and resultingly, there is generated a void 15 at the grain boundary 14. In particular, when the residual tensile stress is concentrated in an area in which the grain boundary 14 intersects with the barrier metal film 12 at a bottom of the via-contact 9, the void 15 grows with the result of disconnection between the lower wiring layer 5 and the via-contact 9. This causes inability of operation of a semiconductor device.
As illustrated in FIG. 3A, residual tensile stress remains in the lower wiring layer 5, the via-contact 9 and the upper wiring layer 13 in a wiring structure fabricated in accordance with a dual damascene process. In particular, since the residual tensile stress is directed toward the upper wiring layer 13 in the via-contact 9, a void 15 is likely to grow in an area in which the grain boundary 14 intersects with the barrier metal film 12 at a bottom of the via-contact 9.
As illustrated in FIGS. 3B and 3C, the residual tensile stress is concentrated in the via-contact 9 in a wiring structure including the via-contact 9 and the upper wiring layer 13 both formed integrally with each other. As a result, a void 15 may be generated at a bottom of the barrier metal film 12, if the copper of which the via-contact 9 is composed makes poor adhesion with the barrier metal film 12, as illustrated in FIG. 3B, or a void 15 may separate the via-contact 9 into two portions, if the grain boundary 14 horizontally extends across the via-contact 9, as illustrated in FIG. 3C. In both cases, the upper wiring layer 13 cannot make sufficient electrical contact with the lower wiring layer 5.
In a wiring structure fabricated in accordance with a dual damascene process, which defect occurs among the defects illustrated in FIGS. 3A to 3C is dependent on whether there exists the grain boundary 14, in what density the via-hole 9a is filled with copper, and other factors. If the via-hole 9a is not sufficiently filled with copper, the defect illustrated in FIG. 3B or 3C would occur rather than the defect illustrated in FIG. 3A.
In order to prevent occurrence of the defects illustrated in FIGS. 3A to 3C, the upper and lower wiring layers 13 and 5 may be designed to have a greater width, or the via-contact 9 may be designed to have a greater aspect ratio.
However, a greater width of the upper and lower wiring layers 13 and 5 and a greater diameter of the via-contact 9 are contrary to a requirement of fabricating a semiconductor device in a possibly smaller size. If the via-contact 9 is designed to have a smaller height, a problem of wiring delay will be caused by a parasitic capacitance between the upper and lower wiring layers 13 and 5.
In order to reduce residual tensile stress in wiring layers and a via-contact to thereby avoid the above-mentioned problems, Japanese Patent Application Publication No. 2001-160590 has suggested a method of fabricating a semiconductor device including the step of annealing copper at a temperature in the range of 80 to 200 degrees centigrade, whereas copper is annealed usually at a temperature in the range of 200 to 400 degrees centigrade.
In a step of heating electroplated copper up to 420 degrees centigrade from a room temperature in the suggested method, it is observed that a stress varies due to diffusion creep in accordance with thermal expansion at a temperature in the range of a room temperature and 200 degrees centigrade, whereas it is observed that a stress is relaxed due to rapid diffusion of copper at a temperature in the range of 200 to 420 degrees centigrade. Relaxation of a stress which occurred at a high temperature remains as it is, even if the plate copper is cooled down to a room temperature. At a room temperature, a wiring layer or a via-contact has a reverse stress, that is, a compressive stress.
According to the Publication, if the electroplated copper is annealed at 200 degrees centigrade or lower, the copper expands in a trench and a via-hole, and simultaneously, copper grain is facilitated to grow and a void is facilitated to be generated, however, by cooling the copper down to a room temperature, the copper is densified and a stress is relaxed with the result that the copper existing in a trench remains unchanged with respect to a volume even after polished by CMP, and that the residual tensile stress can be reduced.
It might be possible to reduce the residual tensile stress in a trench and a via-hole to some degree in accordance with the method suggested in the Publication. However, there is newly caused another problem that if copper is annealed at a temperature in the range of 80 to 200 degrees centigrade, which is lower than a range of a temperature at which copper is usually annealed, the copper would have a smaller diameter, resulting in that there are generated a lot of paths through which the copper is diffused, and a resistance to electromigration is reduced.
In a process of fabricating a semiconductor device, a high-temperature step is carried out a plurality of times for applying plasma to a substrate, or forming an electrically insulating film, for instance. Hence, even if copper is annealed at a relatively low temperature immediately after the copper has been plated into a trench or a via-hole, the residual tensile stress remains as it is in a wiring layer or a via-contact, if a semiconductor device is exposed to a relatively high temperature in a subsequent step. Accordingly, it is suggested in the above-mentioned Publication that steps to be carried out after a step of forming a copper wiring layer are carried out at 400 degrees or lower.
However, such an upper limit in a temperature would render a process of fabricating a semiconductor device complex, and reduce a yield in fabrication of a semiconductor device.